Virtual Workshop on “Next Generation Computing in the Era of Chiplets”

February 29, 2024, 8.20 AM (New York time – EST) – 2.20 PM (Rome time – GMT+1) – 9.20 PM (Singapore time, GMT+8)

Moitreyee Mukherjee-Roy, IBM, USA
Zhu Yao, A*STAR, Singapore
Giovanni Finocchio, University of Messina, Italy

The concepts behind the idea of Chiplets are currently groundbreaking research directions which are paving the way for a new era of innovation where integration of semiconductor technology with emerging technologies will be facilitated. This workshop is co-organized by TC-16 Quantum, Neuromorphic, and Unconventional Computing Technical Committee of NTC, IEEE Magnetics Society – Italy Chapter and Petaspin Association. This virtual workshop is designed to be the starting point of the creation of a community which will bridge innovative concepts of new emerging technology into the game of Chiplets that can be potentially used in transforming fields such as computing, artificial initelligence, Internet of things, etc. It will be a forum to bring together ideas and set the directions to move the topic forward. Save the date and see you there!

To register for the event fill the following form!

Zoom link to join the meeting:
Meeting ID: 852 2716 7200
Passcode: 978499

Program – February 29th, 2024

Title of the talk
Moitreyee Mukherjee-Roy, IBM, USA
Zhu Yao, A*STAR, Singapore
Giovanni Finocchio, University of Messina, Italy
Arvind Kumar, Principal Research Staff Member at the IBM T.J. Watson Research Center – “Chiplets for the future of AI”
Biography: Dr. Arvind Kumar is a Principal Research Staff Member at the IBM Thomas J. Watson Research Center where he manages a team focusing on next generation AI
Hardware including heterogeneous integration. He has presented several invited talks and served as a panelist and short-course instructor in this area at major conferences. He holds over 50 patents and is an IBM Master Inventor. Dr. Kumar earned SB, SM, and PhD degrees in Electrical Engineering and Computer Science, all from MIT, and held an SRC graduate fellowship during his doctoral studies.
Abstract: The explosive growth of AI is accompanied by ever-increasing demands of compute, memory, and bandwidth. Meeting these demands sustainably while logic scaling provides diminishing benefits is well-aligned with the industry movement to chiplets.
In this talk I will discuss the opportunities for heterogeneous integration to meet the challenging demands of AI, examining both the architecture requirements as well as the advanced packaging technologies needed to enable an upward trajectory for system performance.
Martin Beihl, AE Director Cadence Design Systems GmbH – “An EDA perspective on chips transforming into 3D systems”
Biography: “Martin Biehl is AE director at Cadence responsible for the PCB, IC Package and Multi Systems Analysis tools in Europe. Martin holds a PhD in Electrical Engineering from university Karlsruhe Germany. He worked 7 years in a PCB design team at Siemens before joining Cadence in 2005.”
Abstract: To meet today’s demands of increased functional density, higher bandwidths, lower power, smaller form-factors and lower costs, design teams are pivoting from Moore’s Law to More-than-Moore; a world of advanced packaging techniques involving multiple stacked and unstacked chiplets in a single package. Helping to accelerate this trend, the large IC foundries are now competing with the traditional packaging solution providers (OSATs) by providing their own back-end/packaging solutions based on wafer-level manufacturing techniques. The result is an explosion in the number of packaging technologies, and in the process, shifting semiconductor packaging from a necessary evil to a value-add, differentiating technology.  
From this presentation, you will learn about trends in advanced multi-chip(let) architectures, and design challenges for package and IC engineers when migrating to cutting-edge 2.5D and 3D packaging solutions.
Surya Bhattacharya, A*STAR Institute of Microelectronics, Singapore – “Multi-Chiplet Heterogeneous Integration Packaging for Semiconductor System
Biography: Dr. Surya Bhattacharya is Director, System-in-Package, at A*STAR Institute of Microelectronics (IME), Singapore. Over the past 30 years, he has worked on CMOS technology development, high volume product and research institute. At IME, Surya leads the packaging team to initiate and execute industry consortia projects to address challenges in advanced heterogeneous integration for system scaling. Before joining IME he served as Direcotor of Foundry Engineering at Qualcomm, working on technology bring-up and product ramps at leading foundries. Surya has a PhD in Electrical Engineering from the Unviersity of Texas at Austir and B. Tech in Electrical Engineering from the Indian Institute of Technology, Madras.
Abstract: Semiconductor system scaling has been driven by the need to pack increased functionality and performance lower power and into smaller formfactors. In past decades, system scaling was achivied primarily through CMOS chip scaling. Hyper-scale Data Centres, Generative AI, High Performance Compute, Co-packaged optics, Automotive electronics and 5G/6G/SATCOM applications have driven the industry to adopt multi-chip heterogeneous integration (MCHI) packanging to overcome chip-scaling limitatios and meet the demanding a diverse needs of Power-Perfomance- Formfactor- COST (PPFC) driven semiconductor in a single package. In this talk, we will present the challenges and opportunities that the industry encounters along the path to achieving multi-chiplet Trillion transistor packages.